In a NAND type flash memory, in order to reduce a chip area, a charge/discharge transistor which charges or discharge bit lines or a select transistor which selects a bit line may be formed in a well where a memory cell is formed. In this case, during an erase operation for the memory cell, a high voltage may be applied to gate insulating films of the charge/discharge transistor and the select transistor, and thus, destruction of the gate insulating films may occur.